The present invention is directed to a parallel shifter having a minimum time delay and which is useful for both left and right shifting as well as rotation.
When it is desired to translate a binary number from one location in a shift register to another which, for example, might be desirable in floating point arithmetic in a computer storage register, a barrel shifter is useful. This type of switch design is disclosed in an article entitled "A Barrel Switch Design" by R. L. Lim in Computer Design dated August, 1972. Such barrel switch is a tree-type network which utilizes a two layer design configuration to provide for different numbers of shift steps. This tree-type decoding design suffers from time delay and because of the two layer structure is not a true parallel shifter.
Another type of shifter is disclosed in an article entitled "32 Bit High Speed Shifter" by A. Perlowski in the Honeywell Magazine published in St. Petersburg, Fla., dated February, 1972. This is a square matrix type of shifter which while truly parallel in configuration has a very complex circuit configuration.
It is also known that a multiplier can be used as a shifter by the technique of shifting the word X by N steps; for example, shifting N steps to the left is equivalent to performing the multiplication 2.sup.N . X; and shifting right N steps to the right is equivalent to 2.sup.M.sup.-N . X where M is the word length. However, this technique has not been utilized with multipliers because of the inherent layers of time delay.